One application of a Phase Locked Loop (PLL) circuit is in a frequency synthesizer that controls the local oscillator frequency in the front end of an electronically tuned receiver. In this application, the phase locked loop generates the required frequency to mix with the RF energy from the antenna such that the user selected carrier frequency (IF) can be isolated from other signals and detected. Prior Art FIG. 1 shows a phase locked loop in this application, illustrating antenna 10, mixer 12, phaselocked loop 14 and the remainder of the radio signal processing and audio circuitry 16. For optimal receiver performance it is necessary that the resulting local oscillator have the maximum possible spectral purity.
An example of a prior art phase locked loop with desirable performance characteristics is shown in U.S. Pat. No. 4,987,387, Kennedy et al., assigned to the assignee of this invention and having a disclosure that is incorporated herein by reference.
Referring to the FIG. 2, the phase locked loop 14 includes a phase detector (PD) 22, a voltage controlled oscillator (VCO) 62, a reference oscillator 18, a divide by N counter 60, a loop filter (LF) 37 consisting of two stages 36, 58, and a microprocessor 64 for control. The output FREF of reference oscillator 18 is connected to one input of the phase detector 22 to produce the phase comparison frequency. The output signal DIVN of divide by N counter 60 is connected to the other input of phase detector 22. Phase detector 22 compares the phase of the reference frequency FREF and the frequency signal DIVN and produces an output that is proportional to the phase difference between the two signals.
FIGS. 3, 4 and 5 illustrate the operation of the phase detector 22. The rising edge of signal FREF is considered the reference. Referring to a first case scenario in FIG. 3, when the rising edge of DIVN occurs before the rising edge of FREF, the signal SOURCE on line 24 (FIG. 2) goes high, enabling transmission gate 28. As a result, current from current source 32 flows into capacitor 40. The current flow into capacitor 40 causes the voltage Vc40 across capacitor 40 to increase. The amount of voltage created on capacitor 40 is proportional to the phase difference between the inputs FREF and DIVN of phase detector 22.
Referring to a second case scenario in FIG. 4, when the rising edge of FREF occurs before the rising edge of DIVN, the signal SINK on line 26 goes high, enabling transmission gate 30. As a result, current from current source 34 flows out of capacitor 40. The current flow into capacitor 40 causes the voltage Vc40 across capacitor 40 to decrease. The voltage on capacitor 40 is proportional to the phase difference between the inputs FREF and DIVN of phase detector 22.
Referring to a third case scenario in FIG. 5, when the rising edges of FREF and DIVN occur at the same time, there are no SOURCE or SINK pulses and therefore no current flows into or out of capacitor 40. This is the phase locked condition. Phase locked loop 14 operates to obtain the phase locked condition of FIG. 5.
The voltage Vc40 across capacitor 40 is filtered by the switched capacitor loop filter 36 (the first filter stage), comprising amplifier 50, capacitors 44 and 46, transmission gates 38 and 42, and reference voltage generator 48. First filter stage 36 has a pole at 0 Hz, and a higher frequency zero to provide very high gain at dc and unity gain above the zero frequency, essentially acting as an integrator with a zero added to provide stability to the loop and functioning to add up the phase differences of each clock cycle. If the phase of DIVN is far away from the phase of FREF, the output of the loop filter 36 will keep increasing or decreasing until the phase and frequencies become the same.
The voltage (Vs1) on line 39 at the output of first stage 36 is then applied to the second stage 58 of loop filter 37. Second stage 58 comprises resistors 52 and 54 and capacitor 56 and attenuates noise by the ratio (R52+R54)/R54 at frequencies above the zero frequency. The desired signal is also attenuated above the zero frequency. However since the desired steady state signal is a dc voltage, it does not adversely effect the operation of the loop. It is important to note for later reference that the current I2 flowing into capacitor 56 is equal to: EQU (Vs1-Vc56)/(R52+R54). (1)
The output signal TV of the second stage 58 is the tuning voltage control signal that controls the frequency of voltage controlled oscillator 62. The output signal VCO of voltage controlled oscillator 62 is connected to the input of divide by N counter 60. The signal output from divide by N counter 60 has a frequency equal to 1/N times the frequency of the signal VCO. The signal TV forces the frequency of the signal VCO to change in the correct direction until the phase and the frequency of the signals DIVN and FREF are the same. This completes the control loop.
The function of microprocessor 64 is to send the correct divide by N number to divide by N counter 60 for mixing the frequency signal VCO with the RF energy. Details required to implement the above described circuits are known to those skilled in the art.
In implementing a phase locked loop such as the one shown, it is desirable to maintain high loop gain and low noise both of which are very desirable. The characteristics give rise to slew rate limitations, resulting in a relatively long time period (i.e., approximately 40 ms) required to acquire lock when the FREF frequency is far away from the DIVN frequency.
The relatively long lock time is created by the charge rate of capacitor 56, defined as: EQU dVc56/dt=(Vs1-Vc56)/((R52+R54)*C56)). (2)
The Tuning Voltage (TV) is equal to: EQU ((Vs1-Vc56)*R54/(R52+R54)+Vc56). (3)
Long locking time slows radio response time since the radio cannot isolate and detect the user selected carrier frequency until the phase locked loop has acquired lock.
In using on-chip implementations for the above system, the switching capacitor filter is integrated and an external lead-lag network is used. During the larger excursions that occur during channel changes, the on chip op amp very quickly hits the power supply rails due to it's high gain. When this happens the relatively long time constant of the external lead-lag network becomes the limiting factor and it can take a relatively long time to achieve lock.
A new radio format known as RDS (Radio Data System) has software capable of selecting the best available station from a list of stations carrying the same program material. Doing this requires fast frequency hopping to look at each station in the list.